rev 2.1, october 22, 2007 page 1 of 11 400 west cesar chavez , austin, tx 78701 1+(512) 416 - 8500 1+(512) 416 - 9669 www.silabs.com sl2305 ? key features ? 10 to 140 mhz operating frequency range ? low output clock jitter: - 1 4 0 ps - max c -c - j at 66 mhz ? low output -to - output skew: 150 ps - max ? low product - to - product skew: 400 ps - max ? 3.3 v power supply range ? low power dissipation: - 14 ma - max at 66 mhz - 26 ma - max at 133 mhz ? one input drives 5 outputs organized as 4+1 ? spreadthru ? pll that allows use of sscg ? standard and high - drive options ? available in 8 - pin soic and tssop package s ? available in commercial and industrial grades applications ? printers and mfps ? digital copiers ? pcs and work stations ? dtv ? routers, switchers and servers ? digital embeded systems description the sl23 05 is a low skew, low jitter and low power zero delay buffer (zdb) designed to produce up to five (5) clock outputs from one (1) reference input clock for high speed clock distribution applications. the product has an on - chip pll which locks to the input clock at clkin and receives its feedback internally from the clkout pin. the sl23 05 is available with two (2) drive stren gth versions. the - 1 is the standard- drive version and - 1h is the high- drive version. the s l23 05 high- drive version operates up to 140 mhz and t he standard dri ve version - 1 operates up to 100. the sl23 05 enter into power - down (pd) mode if the input at clkin is dc (0 to vdd). in this power - down state all five (5) outputs are tri - stated and the pl l is tu rned off leading to less than 12 a - max of power supply current draw. benefits ? up to five (5) distribution of input clock ? standard and high -d rive levels to control impedance level, frequency range and emi ? low jitter and skew ? low power dissipation ? low cost block diagram pll vdd gnd clkin clkout clk1 clk2 clk3 clk4 low jitter and skew 10 to 140 mhz zero delay buffer (zdb)
rev 2.1, october 22, 2007 page 2 of 11 sl2305 pin configuration 1 2 3 4 8 7 6 5 clkout clk4 vdd clk3 gnd clk1 clk2 clkin pin description 8 - pin soic or tssop pin number pin name pin type pin description 1 clkin input reference frequency clock input. weak pull - down (2 50k). 2 clk2 output buffered cl o ck output weak pull - down (2 50k). 3 clk1 output buffered clock output. weak pull - down (2 50k). 4 gnd power power ground. 5 clk3 output buffered clock output. weak pull - down (2 50k). 6 vdd power 3.3v power supply. 7 clk4 output buffered c lock ou tput. weak pull - down (2 50k). 8 clkout output buffered clock output, used for internal feedback to pll input. weak pull - down (2 50k).
rev 2.1, october 22, 2007 page 3 of 11 sl2305 general description the sl23 05 is a low skew, low jitter zero delay buffer with very low operating power supply cur rent (idd). the product includes an on - chip high performance pll that locks into the input refe rence clock and produces five (5 ) output clock drivers tracking the input reference clock for systems requiring clock distribution. in addition to clkout that is used for internal pll feedback, there is a single bank wi th four (4) outputs , bringing the number of total available output clocks to five (5 ). input and output frequency range the input and output frequency range is the same. but, the frequency range d epends on the drive levels and load capacitance (cl) as given in the below table 1. drive cl(pf) min(mhz) max(mhz) high (- 1h) 15 10 140 high (- 1h) 30 10 100 std (-1) 15 10 100 std (-1) 30 10 66 table 1. input/output frequency range if the input clo ck frequency is dc (0 to vdd) , this is det ected by an input det ection circuitry and all five (5 ) clock outputs are forced to hi - z. the pll is shutdown to save power. in this shutdown state , the product draws less than 12a - max supply current. spreadthru ? feature if a spread spectrum clock (ssc) were to be us ed as an input clock, the sl23 05 is designed to pass the modulated spread spectrum clock (ssc) signal from its clkin ( reference) input to the output clocks. the same spread characteristics at the input are passed through the pll and drivers without any degradation in spread percent (%), spread profile and modulation frequency. high and low - drive product options the sl2305 is offered with high - drive ? - 1h? and standard - drive ? - 1? options. these drive options enable the users to control load levels, frequency range and emi control. refer to the ac electrical tables for the details. skew and zero delay all outputs should drive the similar load t o achieve output - to -out put and input -to - output skew specifications given in the ac electrical tables. however, zero delay between input and outputs can be adjusted by changing the loading of clkout rela tive to the other clock outputs since clkout is the feedback to the pll. po wer supply range (vdd) the sl2305 is designed to operate from 3.0 v (min) to 3.6 v (max), complying with vdd= 3.3v +/ - 10% requirement. an internal on - chip voltage regulator is used to supply pll constant power supply of 1.8v, leading to a consistent and sta ble pll electrical performance in terms of skew, jitter and power dissipation. temperature range and packages the sl2305 is offered with commercial temperature ran ge of 0 to +70 c (c - grade) and industria l temperature range of -40 to +85c (i - grade). the sl2305 is available in 8 - pin soic ( 150 - mil) and 8 - pin tssop ( 173- mil) packages. sl23ep05 refer to sl23ep05 for extended frequency operation from 10 to 220mhz and 2.5v to 3.3v power supply operation range.
rev 2.1, october 22, 2007 page 4 of 11 sl2305 absolute maximum ratings operating conditions: unl ess otherwise stated vdd= 3.3v +/ - 10% and both c and i grades description conditio n min max unit supply voltage, vdd ? 0.5 4.6 v all inputs and outputs ? 0.5 vdd+0.5 v ambient operating temperature in operation, c - grade 0 70 c ambient operating temperature in operation, i - grade ? 40 85 c storage temperature no power is applied ? 65 150 c junction temperature in operation, power is applied ? 125 c soldering temperature ? 260 c esd rating (human body model) jedec22 - a114d - 4,000 4,000 v esd rating (charge device model) jedec22 - c101c - 1,500 1,500 v esd rating (machine mod el) jedec22 - a115d -250 250 v latch -up 125c -200 200 ma symbol description condition min max unit vdd 3.3v supply voltage 3.3v+/ - 10% 3.0 3.6 v ta operating tem perature(ambient) commercial 0 70 c industrial ? 40 85 c cload load capacitance 10 to 140 mhz, - 1h high drive ? 15 pf 10 to 100 mhz, - 1h high drive ? 30 pf 10 to 100mhz, - 1 standard drive ? 15 pf 10 to 66mhz, - 1 standard drive ? 30 pf cin input capacitance clkin pin ? 7 pf tpu power - up time power - up time for all vdds to reach minimum vdd voltage (vdd=3.0v). 0.05 100 ms clbw closed - loop bandwidth 3.3v, (typical) 1.2 mhz zout output impedance 3.3v (typical), - 1h high drive 22 ? 3.3v (typical), - 1 standard drive 32 ?
rev 2.1, october 22, 2007 page 5 of 11 sl2305 dc electr ical specifications: unless otherwise stated vdd=3.3v+/ - 10% and both c and i grades symbol description condition min max unit vdd supply voltage 3.0 3.6 v vil input low voltage clkin (pin -1) ? 0.8 v vih input high voltage clkin (pin -1) 2.0 v dd +0.3 v iil input low current clkin, 0 < vin < 0.8v ? 25 a iih input high current clkin, vin = vdd ? 50 a vol output low voltage (all outputs) iol = 8 ma (standard drive ) ? 0.4 v iol = 12 ma (high drive) ? 0.4 v voh output high voltage (all outputs) ioh = ? 8 ma (standard drive) 2.4 ? v ioh = ? 12 ma (high drive) 2.4 ? v iddpd power down supply current clkin=0 to vdd c - grade, power - down if clkin=0 to vdd or input is floating ? 12 a i - grade, power - down if clkin=0 to vdd or input is floating ? 25 a idd1 power supply current all outputs cl=0, 33 mhz clkin ? 8 ma idd2 power supply current all outputs cl=0, 66 mhz clkin ? 14 ma idd3 power suppl y current all outputs cl=0, 100 mhz clkin ? 20 ma idd4 power supply current all outputs cl=0, 133 mhz clkin ? 26 ma rpd pull - down resistors pins - 1/2/3/5/7/8, 250k - typ 175 325 k
rev 2.1, october 22, 2007 page 6 of 11 sl2305 switching specifications : unless otherwise stated vdd=3.3v+/ - 10% and both c and i grades notes: 1. for the given maximum loading conditions. s ee cl in operating conditions table. 2. parameter is guaranteed by design and characterization. not 100% tested in production. symbol description condition min m ax unit fmax1 maximum frequency (input=output ) [1] all active pll modes high drive ( - 1h). all outputs cl=15pf 10 140 mhz high drive ( - 1h), all outputs cl=30pf 10 100 mhz standard drive, ( - 1), all outputs cl=15pf 10 100 mhz standard drive, ( - 1), all outputs cl=30pf 10 66 mhz indc input duty cycle measured at 1.4v, fout=66mhz, c l=15pf 30 70 % outdc 1 output duty cycle measured at 1 . 4v, fout 50 mhz, cl=15pf [2] 40 60 % outdc 2 output duty cycle measured at 1.4v, fout 50mhz, cl=15pf [2] 45 55 % tr/f rise, fall time (3.3v) (measured at: 0.8 to 2.0v) [2] high drive ( - 1h), cl=10pf ? 1.5 ns high drive ( - 1h), cl=30pf ? 1.8 ns standard driv e ( - 1), cl=10pf ? 2.2 ns standard drive ( - 1), cl=30pf ? 2.5 ns t1 output -to - output skew (measured at vdd/2) [2] all outputs cl=0 or equally loaded, - 1 or - 1h drives ? 150 ps t2 product -to - product skew (measured at vdd/2) [2] all outputs cl=0 or equally loaded, - 1 or - 1h drives ? 400 ps t3 delay time, clkin rising edge to clkout rising edge measured at vdd/2 [2] ? 220 220 ps tplock pll lock time time from 90% of vdd to valid clocks on all the output clocks [2] ? 1.0 ms ccj cycle -to - cycle jit ter fin=fout=66 mhz, rev 2.1, october 22, 2007 page 7 of 11 sl2305 external co mponents & design considerations typical application schematic sl2305 cl cl cl 0.1f clkin clkout clk1 clk4 gnd vdd 1 6 4 7 3 8 comments and recommen dations decoupling capacitor: a decoupling capacitor of 0.1f must be used between vdd and vss on the pins 6 and 4. place the capacitor on the component side of the pcb as close to the vdd pin as possible. the pcb trace to the vdd pin and to the gnd via sh ould be kept as short as possible. do not use vias between the decoupling capacitor and the vdd pin. series termination resistor : a series termination resistor is recommended if the distance between the output s and the load is over 1 ? inch. the nominal im pedance of the clock output s are about 30 . use 20 resistor in series with the output to terminate 50 trace impedance and place 20 resistor as close to the clock outputs as possible. zero delay and skew control: all outputs and clkin pins should be loaded with the same load to achi eve ?zero delay? between the clkin and the outputs. the clkout pin is connected to clkin internally on - chip for internal feedback to pll, and sees an additional 2 pf load with respect to the clock pins. for applications requiring zero input/output delay, t he load at the all output pins including the clkout pin must be the same. if any delay adjustment is required, the capacitance at the clkout pin could be increased or decreased to increase or decrease the delay between clocks and clkin. for minimum pin -to - pin skew, the external load at the clock outputs must be the same.
rev 2.1, october 22, 2007 page 8 of 11 sl2305 switching waveforms output vdd/2 vdd/2 output t 1 input vdd/2 vdd/2 clkout t 2 figure 1. output to output skew figure 2. input - to - output skew t 3 any output part 1 or 2 vdd/2 vdd/2 any output part 2 or 1 figure 3. part -to - part skew
rev 2.1, october 22, 2007 page 9 of 11 sl2305 package outline and package dimensions 8 - pin soic package (1 50- mil) 1 4 8 5 0.150(3.810) 0.157(3.987 0.230(5.842) 0.244(6.197) 0.189(4.800) 0.196(4.978) 0.050(1.270) bsc 0.0138(0.350) 0.0192(0.487) 0.004(0.102) seating plane 0.004(0.102) 0.0098(0.249) 0.061(1.549) 0.068(1.727) 0 to 8 0.010(0.2540) 0.016(0.406) x 45 0.016(0.406) 0.035(0.889) 0.0075(0.190) 0.0098(0.249) pin-1 id dimensions are in inches(milimeters). top line : (min) and bottom line : (max) thermal characteristics parameter symbol condition min typ max unit thermal resistance junction to ambient ja still air - 150 - c/w ja 1m/s air flow - 140 - c/w ja 3m/s air flow - 120 - c/w thermal resistance junction to case jc independent of air flow - 40 - c/w
rev 2.1, october 22, 2007 page 10 of 11 sl2305 package outline and package dimensions 8 - pin tssop package (4.4 - mm ) 1 4 8 5 6.250(0.246) 6.500(0.256) 4.300(0.169) 4.500(0.177) 2.900(0.114) 3.100(0.122) 0.800(0.031) 1.050(0.041) 0.190(0.007) 0.300(0.012) 0.650(0.025) bsc 0.050(0.002) 0.150(0.006) 1.200(0.047) max 0.076(0.003) 0 to 8 0.500(0.020) 0.750(0.030) 0.250(0.010) bsc gauge plane 0.090(0.003) 0.200(0.008) dimensions are in milimeters (inches) top line : (min) and bottom line : (max) pin-1 id seating plane thermal characteristics parameter symbol condition min typ max unit thermal resistance junction to ambient still air - 110 - c/w 1m/s air flow - 100 - c/w 3m/s air flow - 80 - c/w thermal resistance junction to case independent of air flow - 35 - c/w
rev 2.1, october 22, 2007 page 11 of 11 sl2305 ordering information [ 3] ordering number marking shipping package package temperature sl2305sc - 1 sl2305sc - 1 tube 8 - pin soic 0 to 70 c sl2305sc - 1t sl2305sc - 1 tape and reel 8 - pin soic 0 to 70 c sl2305si - 1 sl2305si - 1 tube 8 - pin soic - 40 to 85c sl2305si -1t sl2305si -1 tape and reel 8 - pin soic - 40 to 85c sl2305sc - 1h sl2305sc - 1h tube 8 - pin soic 0 to 70c sl2305sc - 1ht sl2305sc - 1h tape and reel 8 - pin soic 0 to 70c sl2305si -1h sl2305si -1h tube 8 - pin soic - 40 to 85c sl2305si - 1ht sl2305si - 1h tape and reel 8 - pin soic - 40 to 85c sl2305zc -1 sl2305zc -1 tube 8 - pin tssop 0 to 70c sl2305zc - 1t sl2305zc - 1 tape and reel 8 - pin tssop 0 to 70c sl2305zi -1 sl2305zi -1 tube 8 - pin tssop - 40 to 85c sl2305zi -1t sl2305zi -1 tape and reel 8 - pin tssop - 40 to 85c sl2305zc - 1h sl2305zc - 1h tube 8 - pin tssop 0 to 70c sl2305zc - 1ht sl2305zc -1h tape and reel 8 - pin tssop 0 to 70c sl2305zi - 1h sl2305zi - 1h tube 8 - pin tssop - 40 to 85c sl2305zi - 1ht sl2305zi -1h tape and reel 8 - pin tssop - 40 to 85c notes: 3. the sl23 05 products are rohs compliant. the information in this document is believed to be accurate in all respects at the time of publication but is subject to chan ge without notice. silicon laboratories assumes no responsibil ity for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of u ndescribed features or parameters. s ilicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories assume an y liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. silicon laboratories products are not designed, intended, or au thorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratori es product could create a situation where personal injury or death may occur. should buyer purchase or use sili con laboratories products for any such unintended or unauthorized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and d amages.
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